1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, particularly, a modified T-shaped gate electrode.
2. Description of the Related Art
In a field effect transistor, the gate length has been reduced to improve the high frequency performance. That is, when the gate length is reduced, the transit time of carriers within a semiconductor layer is reduced, so that a current cut off frequency f.sub..iota. is increased, thus improving the high frequency performance.
On the other hand, the reduction of the gate length increases the resistance of a gate electrode.
In order to reduce the resistance of a gate electrode, a T-shaped gate electrode has been developed.
In a first prior art method for manufacturing a T-shaped gate electrode, an insulating layer is formed on a semiconductor substrate, and a gate opening is perforated in the insulating layer. Then, a T-shaped gate electrode is formed on the insulating layer having the opening. This will be explained later in detail.
In the first prior art method, however, when the gate length is reduce to increase an aspect ratio of the gate opening, a shadowing effect is caused. As a result, a cavity is generated in the gate electrode. Also, if a gate recess portion is formed in the semiconductor substrate, a disconnection occurs in the gate electrode.
In a second prior art method for manufacturing a semiconductor device, the insulating layer of the first prior art method is made thin to reduce the aspect ratio. Thus, the gate electrode is easily buried in the opening of the insulating layer, to thereby avoid the shadowing effect. This will also be explained later in detail.
In the second prior art method, however, since the insulating layer is thin, a parasitic capacitance formed by the fringe portions of the T-shaped gate electrode and the semiconductor substrate is increased, so that the high frequency performance is deteriorated.
In a third prior art method for manufacturing a semiconductor device (see: JP-A-63-273363), a sidewall silicon nitride layer is formed within the opening of the insulating layer of the first prior art method, and then, a gate electrode is buried in the opening of the insulating layer. Thus, the aspect ratio of the T-shape electrode is substantially decreased. In addition, since the silicon insulating layer under the fringe portions of the T-shaped gate electrode is thick, a parasitic capacitance formed by the fringe portions of the T-shaped gate electrode layer and the semiconductor substrate is decreased, so that the high frequency performance is improved. This will also be explained later in detail.
In the third prior art method, however, particularly, when the gate length becomes smaller than 0.25 .mu.m, it is difficult to deposit the silicon nitride layer homogenously within the opening of the insulating layer. That is, the silicon nitride layer overhangs the opening. As a result, a desirable shape of the sidewall silicon nitride layer cannot be formed, and accordingly, a desirable T-shape of the gate electrode cannot be obtained.